The present invention is concerned with a method for simultaneously fabricating different oxide thicknesses on the same semiconductor substrate. The present invention is especially advantageous when fabricating CMOS semiconductor devices and especially for providing gate oxide insulators of different thicknesses.
An increasing demand exists for providing semiconductor chips having gate oxide layers of varying thicknesses. In fact, the gate oxide thickness is a major concern in terms of reliability considerations when providing integrated circuit devices containing transistors and other circuit elements that operate at differing voltage levels. By way of example, a relatively thin gate oxide of about 40 xc3x85 is typically grown in a conventional 1.8 volt, 0.25 micron process while a relatively thick gate oxide of about 70 xc3x85 is grown in a conventional 3.3 volt, 0.5 micron process.
Device scaling trends have led to low voltage operation with relatively thin gate oxides; whereas, some circuit applications still require a relatively thick gate oxide, such as driver/receiver circuitry at the chip I/O, and some analog output devices. The thick oxide is necessary for the high voltage devices in order to ensure reliability, while the thin gate oxide is desirable for the relatively fast logic devices that use low voltages at the gate. Use of relatively thick oxide for the lower voltage transistors cause poor device performance and significantly decrease the speed.
Moreover, with the trend of trying to put as many different circuits as possible in the same chip to achieve more functionality and/or improved performance (such as Merged logic-DRAM, embedded NVM microcontrols), there are even more different possible combinations for different parts of circuits in the same chip to have different gate oxide thickness to achieve the optimized performance and reliability in the system level.
One prior method of forming different gate oxide thickness on the same substrate involves multiple masking, strip, and oxide formation steps. However, such approach typically significantly increases the overall manufacturing cost and degrades the reliability as well as yield due to the potential resist residues contamination. Besides, the oxide thickness control is more difficult because the thick oxide layer results from the combination of multiple oxide formation cycles.
Another method for providing dual gate oxide thicknesses employs nitrogen implant for retarding the oxidation rate on the thin gate oxide device component, while permitting a thicker oxide to grow where the nitrogen implant has been blocked. However, the use of nitrogen implant alone has resulted in certain problems. For instance, implanting nitrogen at high doses introduces beam damage in the channel region of the device. This damage in turn results in changes in the channel impurity distributions as well as introducing silicon defects which can degrade sub-Vt leakage (off current), gate oxide breakdown voltage as well as reliability.
Low dose of nitrogen implant for thin oxide with n-type dopant (such as As) co-implant for thick oxide is another approach proposed to achieve multi-gate oxide thickness on the wafer. The problem with this process is that it depends on the dopant to enhance the oxidation rate which limits the freedom of usage because the dopant at the same time determines the substrate concentration which is a very important parameter in the device structure.
It has also been suggested to implant relatively high concentrations of fluoride ion into selected areas of a semiconductor substrate in order to increase or enhance oxide growth in those areas. The relatively high fluoride ion concentrations promote higher oxidation rates primarily through silicon damage. Moreover, use of fluoride ions are problematic since such are not compatible, for instance, with boron-doped PFET gates, as currently used in advanced logic CMOS. In particular, fluorine promotes penetration or diffusion of boron ions into the gate oxide. Accordingly, using fluoride ions as discussed in U.S. Pat. No. 5,480,828 is not especially suitable for advanced CMOS from a practical application viewpoint.
More recently, an improved process for simultaneously fabricating different oxide thicknesses on the same semiconductor substrate employs implanting chlorine and/or bromine ions into areas of a semiconductor substrate where silicon oxide having the highest thicknesses is to be formed. This improved fabrication technique is the subject matter of U.S. patent application Ser. No. 09/090,735 filed Jun. 4, 1998, entitled xe2x80x9cMethod for Fabricating Different Gate Oxide Thicknesses within the Same Chipxe2x80x9d to Ronsheim and assigned to International Business Machines Corporation, the assignee of this application, disclosure of which is incorporated herein by reference.
Although this latter process represents a significant improvement, there still exists room for improvement.
The present invention provides a process for simultaneously fabricating different oxide thicknesses on the same semiconductor substrate that overcome problems of prior suggested techniques.
The present invention makes it possible to increase or extend the range of differences in thicknesses between thicker and thinner silicon dioxide layers. According to the present invention, at least two different ions are used, one being nitrogen and the other being chlorine and/or bromine. The nitrogen is used in those areas where a slower or reduced oxidation rate is desired, while chlorine and/or bromine is used in those areas where a faster oxidation rate is desired. By employing the chlorine and bromine, the dosage of the nitrogen used can be lower than that required by prior art processes. This in turn, significantly reduces, if not entirely eliminates, problems discussed above due to nitrogen doping.
According to the present invention, chlorine and/or bromine implants are employed to affect the thick oxide device regions, which are the non-critical gate dielectrics instead of the relatively thin gate oxide regions. The thin gate oxide uniformity is critical especially as the oxides are scaled to 25 xc3x85 and less. Accordingly, controlling the thickness of thin gate oxide regions is achieved according to the present invention by employing nitrogen implants.
More particularly, the present invention is concerned with a method for simultaneously fabricating different oxide thicknesses on the same semiconductor substrate. The method of the present invention comprises forming a sacrificial layer on the surface of the semiconductor. Chlorine and/or bromine ions are implanted through the sacrificial layer into areas of the semiconductor substrate where silicon dioxide having the higher thicknesses is to be formed. It is preferred according to the present invention that the chlorine and/or bromine ions be implanted at relatively low energy levels and modest dosage levels. In particular, the chlorine and/or bromine ions are typically implanted at a dose of about 2xc3x971013 to 2xc3x971015 atoms/cm2 and at an energy of about 1 to about 15 keV.
Nitrogen ions are implanted through the sacrificial layer into areas of the semiconductor substrate where silicon dioxide having the thinner thicknesses is to be formed. It is preferred according to the present invention that the nitrogen ions be implanted at relatively low energy levels and modest dosage levels. In particular, the nitrogen ions are typically implanted at a dose of about 2xc3x971013 to about 2xc3x971015 atoms/cm2 and an energy of about 1 to about 15 keV.
The particular sequence of the implanting steps is not crucial and can be carried out in any order.
Moreover, according to the present invention, when more than two oxide thicknesses are desired, more than one nitrogen and/or chlorine and/or bromine implantation step can be employed with different dosages of nitrogen and/or chlorine and/or bromine. This makes it possible to tailor and fine tune many silicon dioxide thicknesses as is desired on the substrate. Furthermore, if desired, areas of the substrate where silicon dioxide is to be formed can be left undoped to achieve one more different gate oxide thickness.
After the ions are implanted, the sacrificial silicon dioxide layer is removed and a layer of silicon dioxide is then grown by thermal oxidation on the surface of the semiconductor substrate. The growth rate of the silicon dioxide in the regions containing the chlorine and/or bromine implanted ions is greater than the growth rate in regions not containing the implanted chlorine and/or bromine ions and therefore the silicon dioxide layer will be thicker in those areas compared to the silicon dioxide layer in the areas not containing the implanted chlorine and/or bromine ions.
Similarly, the growth rate of the silicon dioxide in the regions containing the nitrogen implanted ions is less than the growth rate in regions not containing the implanted nitrogen ions and therefore the silicon dioxide layer will be thinner in those areas compared to the silicon dioxide layer in the areas not containing the implanted nitrogen ions.
In addition, the present invention is concerned with a semiconductor substrate having different oxide thicknesses thereon obtained by the above method.
Also, the present invention is concerned with a semiconductor substrate having nitrogen doping in selected areas thereof, chlorine and/or bromine doping in other selected areas thereof and thermally grown silicon oxide layers on the substrate having different thicknesses, wherein the silicon dioxide layer in the regions located above those areas having the chlorine and/or bromine doping is thicker than the silicon dioxide layer in areas above the semiconductor substrate that do not include the chlorine and/or bromine doping, and wherein the silicon dioxide layer in the regions located above those areas having the nitrogen doping is thinner than the silicon dioxide layer in areas above the semiconductor substrate that do not include the nitrogen doping.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.